1. Technical Field
This disclosure relates to clock tree synthesis (CTS). More specifically, this disclosure relates to dual-structure CTS.
2. Related Art
CTS refers to the process of creating a clock distribution network for distributing a clock signal to a set of sequential circuit elements in a circuit design. A circuit design may include multiple clock domains, and each clock domain can include multiple clock trees. The quality of the clock trees that are generated by CTS can have a significant impact on downstream stages in the EDA flow, especially on timing closure. Hence, what are needed are systems and techniques for CTS that can efficiently create high quality clock trees.